Model a comparator behaviorally
The Comparator block is an abstracted behavioral model of a comparator integrated circuit. It does not model an internal transistor-level implementation. Therefore, the block runs quickly during simulation but retains the correct I/O behavior. The block models differential inputs electrically as having infinite resistance and a finite or zero capacitance.
The block models the gate output as a voltage source driving a series resistor and a capacitor that connects to ground. The output pin connects to the resistor-capacitor connection node. If the difference in the inputs is greater than the input threshold voltage, then the output is equal to the High level output voltage ( ). Otherwise, the output is equal to the Low level output voltage ( ).
The output model is shown in the following illustration.
Modeling of the output as a controlled voltage source is representative of a totem-pole or push-pull output stage. To model a device with an open-collector:
Connect the output pin to the base of an NPN Bipolar Transistor or PNP Bipolar Transistor block.
Set the Output resistance parameter to a suitable value.
The voltage which the difference in the input voltages must be greater than so that the comparator gives a logic output 1. The default value is 5 mV.
You can usually find this capacitance value on a manufacturer datasheet. The default value is 0 pF. Setting this value to zero can result in faster simulation times.
The steady-state output voltage, , when the voltage difference across the inputs is less than or equal to the threshold voltage, and the output current is zero. The default value is 0 V.
The steady-state output voltage, , when the voltage difference across the inputs is greater than the threshold voltage, and the output current is zero. The default value is 5 V.
This parameter is the ratio of output voltage drop to output current. Set this parameter to , where is the reduced output high voltage when the output current is . The default value is 50 Ω.
Set this value based on the high-to-low and low-to-high propagation delays. The default value is 0 s.
This block has the following ports: