Filter Design HDL Coder

Testing and Synthesizing Generated HDL Code

You can simulate and test the generated HDL code using the automatically generated VHDL and Verilog test benches. A MATLAB script can be generated for cosimulation using Link for ModelSim or Link for Cadence® Incisive® software (both available separately). This script automates the direct cosimulation of your filter design and the generated code, simplifying the task of comparing and verifying the results of the generated HDL code with the original filter design. This option enables you to utilize the advanced analysis and visualization capabilities of MATLAB to test, debug, and verify the HDL implementation of your filter designs.

Architectural Optimizations

After quantizing the filter, you can use dialogs to invoke Filter Design HDL Coder and configure it with optimization, content, style, and test bench options for your filter application. Supported optimizations include:

  • Canonical signed digit (CSD), for optimizing coefficient multiplier operations in the filter to reduce the area used and maintain or increase clock speed
  • Speed vs. area tradeoff, for exploring hardware architectures for tradeoff between the chip area and the circuit operating frequency
  • Distributed arithmetic (DA), for implementing FIR filters through a DA architecture without using multipliers
  • In addition, Filter Design HDL Coder generates synthesis scripts that accelerate your synthesis work flow.
FD HDL ModelSim

ModelSim simulation results of the fifth-order Butterworth filter and the original filter specification results from DSP System Toolbox. Automatically generated ModelSim test benches simplify and speed up the testing and verification of the VHDL and Verilog code generated by Filter Design HDL Coder.

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FPGA and ASIC Verification Made Easy

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