Simulink Design Verifier

Model Coverage Analysis

Simulink Design Verifier analyzes algorithms and logic in your Simulink and Stateflow models to generate test cases and parameters required by industry standards for developing high-integrity systems. Test generation for structural coverage criteria includes condition, decision, and modified condition/decision coverage (MC/DC).

Test Generation

Test generation for model coverage augments requirements-based tests created by hand or collected during simulation of the complete system. With this approach, Simulink Design Verifier takes existing model coverage information and generates additional test vectors that meet all the coverage objectives not satisfied during requirements-based testing.

Requirements-Based Testing 5:02
Generate test cases from models of system requirements using Simulink Design Verifier™.

You can use these test vectors to better understand missing requirements and to create a more complete test harness. To simplify testing of models with a large number of inports and outports, Simulink Design Verifier identifies unused signals and automatically removes them from the test harness.

All the generated test vectors are captured as a MATLAB structure that can be used directly as input for the test execution in simulation, SIL, or PIL. The collected test data can also be used to generate a test harness model.

Extend Existing Test Cases to Achieve Full Model Coverage 2:42
Leverage existing test cases and achieve full coverage using formal methods for test generation in Simulink Design Verifier™.

Validation of Generated Test Vectors

To validate generated test vectors that meet structural coverage criteria, you can use the Model Coverage tool provided in Simulink Verification and Validation. It monitors simulation and measures whether the objectives reported during formal analysis have been achieved. In addition to coverage objectives for condition, decision, and MC/DC coverage, the Model Coverage tool also reports on the coverage of test objectives, proof objectives, assumptions, constraints, lookup tables, and signal ranges recorded during simulation.

Simulink Design Verifier is certified by TÜV SÜD for use in development processes that must comply with the ISO 26262, IEC 61508, or EN 50128 standards.

Visual display of a generated test vector that activates previously untested functionality.

Visual display of a generated test vector that activates previously untested functionality.

Analysis of Test Coverage on Generated Code

Simulink Design Verifier provides test automation functions for automating the execution of generated test cases against code in SIL and PIL. Code verification functions in Simulink Design Verifier require Embedded Coder. During text execution, you can integrate the code coverage tools available in Embedded Coder for collecting code coverage.

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